The design and manufacture of highly complex electronic circuits, referred to as very-large-scale integrated (“VLSI”) circuits involves many stages. A typical System-on-ship (“SoC”) or chip design begins with the broad characteristics of each circuit of the SoC in terms of inputs and outputs. This broad conceptual design is then refined into an architectural design that shows the major functional units of each circuit and the interactions between these units. Each unit is then designed at a more detailed but still abstract level, typically using logic gates that perform the functions as appropriate to the design. The logic gate specification is then converted into an integrated-circuit (“IC”) layout that is subsequently used to manufacture the chip. Following design, the IC layout is passed to manufacturing for use in producing chips.
Between the design and the manufacturing specification are the analysis and synthesis tools that ensure correct functioning of the chip manufactured from the IC design. The analysis tools are used to detect local layout errors such as design-rule violations, and more global design errors such as logical failures, short-circuits, and power inadequacies, for example. One fundamental analysis technique used by designers involves analysis of the signal timing associated with the IC layout.
Timing constraints typically demand that each transistor of an IC design switch correctly within finite pre-specified time windows, where the finite time windows are pre-partitioned based on the delays of each component in the circuit. The sub-100 nanometer (“nm”) SoC designs running at 1 gigahertz (“GHz”) or faster clock speeds, for example, require a transistor to complete a switching event of approximately 100 picoseconds in length during a timing window of only a few hundred picoseconds. As such, the high-speed associated with typical SoC designs has narrowed the timing windows to extremely small windows.
The small timing windows are very sensitive to the physical dimensions of the devices and the corresponding interconnects, especially in sub-100 nm SoC designs. Consequently, changes to critical physical dimensions of the fabricated circuits introduced into the circuits by the manufacturing process adversely affect the timing windows. As an example, resolution enhancement techniques (“RET”) performed as part of the manufacturing process induces significantly longer transistor switching times because it induces deviations of the poly gate lengths from the designed sizes. Another example is associated with Chemical Mechanical Polishing (“CMP”), which also induces significantly longer wire delay times as a result of dishing effects produced on dense interconnects. Thus, most if not all reported device and interconnect designs adopted in SoC products have noted deviations in physical dimensions as a result of the current design and manufacturing process flow, with many of the deviations being severe.
The design and manufacturing process of chips is expected, however, to ensure delivery of low cost chips through high yield fabrication processes in spite of the issues associated with design deviations introduced during the process. However, the timing issues described above force the circuit designers and manufacturing engineers to sacrifice these criteria and over-design the chips in order to guard band timing constraints. For example, additional buffers are often inserted in the middle of “critical paths” by designers to improve negative slack times. These over-designs complicate the circuit description database, which in turn increases fabrication costs, increases the size of chip areas on a wafer, and reduces chip yield.
A primary cause of the failure of the chip manufacturing process to meet the above-stated objectives relates to a gap in the infrastructure of the semiconductor industry's typical design-manufacture flow. In essence, the timing verification, which is performed during the design stage before tape-out, and the geometry verification, which is performed after tape-out, are each performed in isolation and without any cross-referencing. Therefore, the transistor models and circuit netlists used in the timing analysis or verification are not a part of the documentation provided to the manufacturing process. Likewise, the final silicon images printed on the wafers are not provided to the designers in abstract model formats. Consequently, there is a need for an integrated design-manufacturing process that bridges the gap between design and manufacturing by incorporating the results of both timing and geometry analyses/verifications into the IC design process.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the FIG. number in which that element is first introduced (e.g., element 102 is first introduced and discussed with respect to FIG. 1).